1 of 8 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? unlimited write cycles ? low - power cmos operation ? read and write access times of 100ns ? lithium energy so urce is electrically disconnected to retain freshness until power is applied for the first time ? optional industrial (ind) temperature range of - 40 c to +85c pin assignment pin description a0 ? a19 - address inputs dq0 ?dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+3.3v) gnd - ground nc - no connect description the ds1265w 8mb nonvolatile (nv) srams are 8,388,608 - bit, fully static, nv sra ms organized as 1,048,576 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry that constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatical ly switched on and write protection is unconditionally enabled to prevent data corruption. there is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. ds1265w 3.3v 8mb nonvolatile sram 19 - 5617; rev 11/1 0 www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 35 36 - pin encapsulated package 740mil extended a18 a14 a7 a6 a5 a4 a3 a2 a0 a1 v cc a19 nc a15 a17 we a13 a8 a9 a11 oe a10 dq7 ce 36 34 33 3 2 31 30 29 28 27 26 25 23 24 nc a16 a12 nc dq0 dq1 15 16 22 21 dq6 dq5 17 18 gnd dq2 dq3 dq4 19 20
ds1265w 2 of 8 read mode the d s1265 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 20 address inp uts (a 0 ? a 19 ) defines which of the 1,048,576 bytes of data is accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than t acc . write mode the ds1265 devices execute a write cycle whenever we and ce signals are active ( low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control s ignal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled ( ce and oe active), then we will disable the outputs in t odw from it s falling edge. data - retention mode the ds1265w provides full functional capability for v cc greater than 3.0v and write protects by 2.8v. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams consta ntly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become ?don?t care,? and all outputs become high - impedance. as v cc falls below approximately 2.5v, a power - switching circuit connects the lit hium energy source to ram to retain data. during power - up, when v cc rises above approximately 2.5v, the power - switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 3.0v . freshness seal each ds1265 device is shipped from dallas semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for batter y backup operation.
ds1265w 3 of 8 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +4.6v operating temperature range commercial: 0c to +70c ind ustrial: - 40c to +85c storage temperature range - 40c to +85 c lead temperature (soldering, 10 s ) +260 c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or any other c onditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time ma y affect reliability. recommended dc operating conditions ( t a : see note 10 ) parameter symbol min typ max units notes power - supply voltage v cc 3.0 3.3 3.6 v logic 1 input voltage v ih 2.2 v cc v logic 0 input voltage v il 0.0 +0.4 v dc electrical characteristics (t a : see note 10 ; v cc = 3.3v 0.3v) par ameter symbol min typ max units notes input leakage current i il - 2.0 +2.0 a i/o leakage current i io - 2.0 +2.0 a output current at 2.2v i oh - 1.0 ma output current at 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 150 250 a standby current ce = v cc - 0.2v i ccs2 100 150 a operating current i cco1 50 ma write protection voltage v tp 2.8 2.9 3.0 v capacitance ( t a = +25 c) parameter symbol min typ max units notes input capacitance c in 10 20 pf input/output capacitance c i/o 10 20 pf
ds1265w 4 of 8 ac electrical characteristics (t a : see note 10 ; v cc = 3.3v 0.3v) parameter symbol ds1265w - 100 units notes mi n max read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 o utput high - z from deselection t od 35 ns 5 output hold from address change t oh 5 ns write cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 20 n s ns 12 13 output high - z from we t odw 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 20 n s ns 12 13 timing diagram: read cycle see note 1
ds1265w 5 of 8 timing diagram: write cycle 1 timing diagram: write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13
ds1265w 6 of 8 power - down/power - up condition see note 11 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = + 25 c) parameter symbol min typ max units notes expected data - retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is hi gh for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as the logical and of ce or we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a hig h - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high - impedance state during this period. 8. if we is low or the we low transition occurs prior to, or simultaneously with, the ce low transition, the output buffers remain in a high - impedance state during this period.
ds1265w 7 of 8 9. each ds1265w has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are vali d over the full operating temperature range. for commercial products, this range is 0 c to+ 70 c. for industrial products (ind), this range is - 40 c to +85 c. 11. in a power - down condition, the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured fr om ce going high. 14. ds1265 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions ac test conditions outputs open output load: 100pf + 1ttl gate cycle = 200ns for operating current input pulse levels: 0 to 2.7v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply to lerance pin - package speed grade (ns) ds1265w - 100+ 0c to +70c 3.3v 0.3v 36 740 edip 100 ds1265w - 100ind+ - 40c to +85c 3. 3v 0.3v 36 740 edip 100 + denotes a lead (pb) - free/rohs - compliant package . package information for the latest package ou tline information and land patterns, go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but t he drawing pertains to the package regardless of rohs status . package type package code outline no. land pattern no. 36 edip mdt36+1 ? 21- 0245
ds1265w 8 of 8 revision history revision date description pages changed 11/10 u pdated the storage information, soldering temperature, and lead temperature informatio n in the absolute maximum ratings section; removed the - 15 0 min/max information from the ac electrical characteristics table; updated the ordering information table (removed - 150 parts and leaded - 100 parts); replaced the package outline drawing with the p ackage information table 1, 3, 4, 7
|
